Education background
Bachelor of Metal Materials Science and Engineering, Jilin University of Technology, Changchun, China, 1993;
Master of Computer Science, Hefei University of Technology, Hefei, China, 1997;
Ph.D. in Computer Science, Tsinghua University, Beijing, China, 2001.
Areas of Research Interests/ Research Projects
Computer Architectures, Many-Core Processor, Parallel Compiling and Optimization
Network on Chip
National 863 High-Tech Program: Research on Cache Techniques and Parallel Optimization for Chip Multi-Processor Systems (2008-2010).
Research Status
My research group addresses fundamental problems in cache techniques and optimization for chip multi-processors. Currently I am also developing a simulator which is able to evaluate memory sub-systems quantitatively.
Our simulator, called TSIM (Tsinghua SIMulator), is a fast and cycle-accurate memory sub-system modeling and evaluating framework for Chip Multi-Processors (CMPs). This simulator provides a flexible and extensible approach to evaluating architecture designs, models, and algorithms, including network-on-chip interconnection, cache hardware pre-fetcher, memory system protocol, replacement policy, etc.
TSIM tries to balance among speed, accuracy and flexibility. By introducing the concept of statistical metamerics, TSIM separates the analysis stage from the simulation process. This provides a great facilitation for users to sample and analyze the performance metrics. More significantly, TSIM focuses on CMP systems and supports multithread workloads. A TSIM user is able to freely configure simulation parameters such as cache level, cache size, block size, number of cores, and the replacement policy.
Academic Achievement
[1] Yu Chen, Junmin Lin, Lin Qiao, Zhizhong Tang. SAGA: A stream attribute guided cache allocation policy for microprocessors. Chinese Journal of Computers, vol. 31, no. 11, pp. 1929-1937, 2008 (in chinese).
[2] Shengmei Li, Lin Qiao, Zhizhong Tang, Buqi Cheng, Xingyu Gao. Performance characterization of SPEC CPU2006 benchmarks on Intel and AMD platform, Proc. 2009 Intl. Workshop on Education Technology and Computer Science (IECS2009), Wuhan, China, 2009, Vol. 2, pp. 116-121.
[3] Wei Wang, Lin Qiao, Guangwen Yang, Zhizhong Tang. Performance analysis of the 2-D networks-on-chip. Journal of Computer Research and Development, vol. 46, no. 10, pp. 1601-1611, 2009 (in chinese).
[4] Shengmei Li, Xingyu Gao, Buqi Cheng, Lin Qiao, Zhizhong Tang. Principal component linear regression analysis on performance of applications. Journal of Computer Research and Development, vol. 46, no. 11, pp. 1949-1955, 2009 (in chinese).
[5] Mingliang Liu, Lin Qiao, Yu Chen, Fucen Zeng, Chao Zhang. An extensible memory simulation framework for chip multi-processors. Proc. 2nd Intl. Conf. on Computer Science and Software Engineering (CSSE2009), Wuhan, China, 2009.
[6] Wei Wang, Lin Qiao, Guangwen Yang, Zhizhong Tang. Performance Analysis of the Extended 2-D Grid Interconnection Networks-On-Chip. Journal of Tsinghua University (Science and Technology), vol. 50, no. 1, pp. 161-164, 2010 (in chinese).
[7] Wei Wang, Lin Qiao, Guangwen Yang, Zhizhong Tang. A Kind of Hierarchical Ring Interconnection Networks-on-Chip. Chinese Journal of Computer, vol. 33, no. 2, pp. 326-334, 2010 (in chinese).
[8] Wei Wang, Lin Qiao, Guangwen Yang, Zhizhong Tang. Performance Analysis of the 2-D Networks-On-Chip for Local Uniform Random Communication Pattern. Journal of Computer Research and Development, vol. 47, no. 3, pp. 532-540, 2010.
