Education background
Bachelor of Computer Science & Technology, Harbin Institute of Technology, Harbin, China, 1985;
Master of Semiconductor Physics & Device, Harbin Institute of Technology, Harbin, China, 1987;
Ph.D. in Mechantronic Control & Automation, Harbin Institute of Technology, Harbin, China, 1996;
Post-Doctoral Fellow, State Key Lab of CAD & CG, Zhejiang University, Hangzhou, China, 1999.
Social service
Department of Computer Science & Technology, Tsinghua University: Section Chief of Graduate Students (2000-2003);
Department of Computer Science & Technology, Tsinghua University: Director of EDA Lab (2000-2008);
ACM/IEEE ASP-DAC: Program Committee Member (2010-2011);
Science and Technology Committee of Haidian District of Beijing City: Expert Committee Member (2003-);
Joint Conference of Information Science: Program Co-chair and Advisory Committee Member (2007-2008);
Waseda University: Visiting Scholar, Visiting Professor (2007-2009);
The Chinese University of Hong Kong: Associate Researcher.
Areas of Research Interests/ Research Projects
VLSI Physical Design, SOC Design and Packaging
Optimization Algorithm and its Applications
Application-Specific Architecture Design and Chip Design
"Tsinghua University-Waseda University" International Cooperation Project: SoC Design and Automation (2006-);
"Tsinghua University-Toshiba" International Cooperation Project: Research on Physical Design of Analog Circuit (2007-2010);
National Natural Science Foundation of China: Programmable and Configurable SoC Architecture and Key Technologies (2006-2008);
National Natural Science Foundation of China: Solution Space Smoothing and its Application in Floorplanning and Interconnection Resources Planning (2005-2007);
National Natural Science Foundation of China: Research on Floorplanning and Placement of Mixed Signal SoC (2004-2006);
Joint Project of National Natural Science Foundation and Hong Kong RGC: Research on Least-Flexibility First Optimization Algorithm and its Applications (2003-2005);
"Tsinghua University-Seiko (Jedat)" International Cooperation Project: Layout Automation of Analog Circuits (2002-2005).
Research Status
My research group addresses fundamental problems in VLSI physical design, and has proposed many novel algorithms in this area. Some of them have been successfully embedded in the EDA tools of Japanese or American companies. Based on the achievements of my group, FAIST (Foundation for Advancement of Industry, Science and Technology) of Kitakyushu and Waseda University co-founded an EDA research base for my department in 2006. It is located in Kitakyushu Science and Research Park, and I have been the PI of this cooperation research base since then.
To solve the problem of floor planning and placement, my group has proposed a novel non-slicing floorplan representation: CBL (Corner Block List). This representation is extended to cover the optimal solution and an ergodic neighborhood transformation is proposed. Based on these, my group also proposed many algorithms to solve various constraints in floorplanning and placement. A novel fixed-outline zero-dead-space floorplanning algorithm is also proposed. It has become the new key basic technology to solve hard problems in physical design of floorplacement. Some of these algorithms have been used in EDA tools.
My group has also invented two new optimization algorithms. One is the search space smoothing algorithm that can search in the solution space using both global and local smoothing effects. The other is less-flexibility first algorithm. The two algorithms have been used to solve floorplanning, 3D packing and FPGA floorplanning problems.
Mixed signal SoC physical design and its automation has been virgin soil in EDA area. My group has proposed a novel signal flow method which includes many algorithms to address this challenge. These algorithms include layout constraints automatic extraction, constraints automatic grading, and constraint-driven automatic layout with consideration of symmetry, mismatch, group, signal sensitivity, thermal, etc. The algorithms have been embedded in the EDA tools of Japanese and American companies.
My group also proposed algorithms on FPGA planning, 2.5D and 3D integration, thermal planning for high density integration, X-and-Y interconnection architecture planning, BUS planning, multi-voltage system optimization, and network-on-chip optimization.
Honors And Awards
Science and Technology Progress Award by City of Beijing, Second Class-SOC Physical Design CAD Technology and Applications (2007);
Nature Science Award by Ministry of Education, Second Class-Research on Optimization and Verification of VLSI Physical Design (2006);
"Lin Feng" Award for Education and Management of Graduate Students by Tsinghua University, First Class (2002).
Academic Achievement
[1] Xu He, Sheqin Dong, Yuchun Ma, Signal Through-the-Silicon Via Planning and Pin Assignment for Thermal and Wire Length Optimization in 3D ICs, Integration, the VLSI Journal. 2010
[2] Bei Yu(*), Sheqin Dong, et al, Voltage and Level-Shifter Assignment Driven Floorplanning,IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences,Vol. E92-A, No.12, Dec.2009
[3] Yaoguang Wei, Sheqin Dong, Xianlong Hong, APWL-Y:an accurate and efficient wirelength estimation technique for hexagon/triangle placement, Integration, the VLSI Journal, Integration, the VLSI Journal, 40 (2007), p406-419
[4] Chen S, Dong SQ, Hong XL, Yici Cai, Chung-Kuan Cheng, Jun Gu, "VLSI block placement with alignment constraints", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 53 (8): 622-626 AUG 2006
[5] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, "An Integrated Floorplanning with an Efficient Buffer Planning Algorithm", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 24 (No. 4) (2005)
[6] Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, C.K. Cheng, Jun Gu, "Non-slicing Floorplan and Placement using Corner Block List Topological Representation", IEEE Transaction on CAS, Vol. 51 (No. 5) (2004), pp228-233
[7] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, "Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks", ACM Transactions on Design Automation of Electronic Systems, Vol. 9 (No. 2) (2004), p199-211
[8] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, "Floorplanning with Abutment Constraints Based on Corner Block List", Integration, the VLSI Journal, Vol. 31 (No. 1) (2001), p65-77
[9] Sheqin Dong, Xianlong Hong, Song Chen, Xing Qi, Ruijie Wang, "VLSI Module Placement with Preplaced Modules and Considering Congestion Using Solution Space Smoothing", IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E86-A, (No.12) (2003), pp3136-3147
[10] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, "VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation", IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A (No. 11) (2001), p2697-2704
[11] Bei Yu, Sheqin Dong, et al, Floorplanning and Topology Generation for Application-Specific Network-on-Chip,ACM/IEEE ASP-DAC 2010,
[12] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K.Cheng, Bus Via Reduction Based on Floorplan Revising, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
[13] Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto, A Revisit to Voltage Partitioning Problem, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
[14] Wentao Sui, Sheqin Dong, Jinian Bian, Wirelength-Driven Force-Directed 3D FPGA Placement,ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
[15] Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto, Fixed Outline Multi-Bend Bus Driven Floorplanning,ACM/IEEE ISQED 2010, USA,
[16] Xu He, Sheqin Dong,Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning, ACM/IEEE ISQED 2009, USA, pp740-745
[17] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K. Cheng, A Novel Fixed outline Floorplanner with Zero Deadspace for Hierarchical Design, ACM/IEEE International conference on CAD, 2008, USA,pp16-23
[18] Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang (Tsinghua Univ., China), Satoshi Goto (Waseda Univ., Japan), Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology, The 13th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2008), Korean, January,2008
[19] Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong, "Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation" The 12th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2007), Yokohama, Japan, 2007.1
[20] Hongjie Bai, Sheqin Dong, Xianlong Hong, Congestion driven buffer planning for X-Architecture, ACM/IEEE ISQED 2007, USA,pp835-840
[21] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, "Fast Custom Instruction Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design", IEICE Trans. Fundamentals, Vol. E91-A, No.6, pp. 1478-1487, June 2008.
[22] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, "Exploring Partitions based on Search Space Smoothing for Heterogeneous Multiprocessor System", IEICE Trans. Fundamentals, Special Section on Nonlinear Theory and its Applications, Vol. E91-A, No.6, pp.2456-2464, Sep.2008.
[23] Hong Xianlong, Ma Yuchun, Dong Sheqin, Cai Yici, C.K. Cheng, Jun Gu, "A Floorplanning Representation Corner Block List and The Corner Block List Based Floorplanning Algorithm with Boundary Constraint", SCIENCE IN CHINA (Series F), Vol. 47 (No. 1) (2004), p1-19
[24] Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, "A Buffer Planning Algorithm for Chip-Level Floorplanning", SCIENCE IN CHINA SERIES F-INFORMATION SCIENCES 47 (6): 763-776 DEC 2004
[25] Yuchun Ma, Xianlong Hong, Sheqin Dong, C.K.Cheng, Jun Gu, "General Floorplans with L/T-shaped blocks using corner block list", Journal of Computer Science and Technology vol.21, no. 6, Nov,2006 pp.922-926
[26] Dong Sheqin, Hong Xianlong, Wu Youliang, Gu Jun, "Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle", Journal of Computer Science and Technology (JCST), Vol. 18 (No. 6) (2003), p739-746
[27] Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, C-K Cheng, Jun Gu, "Fast Evaluation of Bounded Slice-line Grid", Journal of Computer Science and Technology (JCST), Vol. 19 (No. 6) (2004), p973-980
[28] Sheqin Dong, Shuo Zhou, Xianlong Hong, Chungkuan Cheng, Jun Gu, Yici Cai, "An Optimum Placement Search Algorithm Based on Extended Corner Block List", Journal of Computer Science and Technology (JCST), Vol. 17 (No. 6) (2002), p699-707
[29] Di Long; Xianlong Hong; Sheqin Dong;"Signal-path driven partition and placement for analog circuit" Design Automation, 2006. Asia and South Pacific Conference on 24-27 Jan. 2006 Page(s):6
[30] Renshen WANG, Sheqin DONG Xianlong HONG, "An Improved P-admissible Floorplan Representation Based on Corner Block List", 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1115-1118
[31] Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu, "LFF Algorithm for Heterogeneous FPGA Floorplanning", 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1123-1126
[32] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, "An Integrated Floorplanning with an Efficient Buffer Planning Algorithm", 2003.3, ACM/SIGDA International Symposium on Physical Design, USA
[33] Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C-K Cheng, Jun Gu, "Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis", 2003.6, IEEE/ACM 40th Design Automation Conference, Los Angeles, USA, p 806-811
[34] Shuo Zhou, Sheqin Dong, Xianlong Hong,Yici Cai, C-K Cheng, Jun Gu, "ECBL: An Extended Corner Block List with Solution Space including Optimum Placement", 2001.3, ACM/SIGDA International Symposium on Physical Design, USA, pp150-155
[35] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, "Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List", 2001.6, IEEE/ACM 38th Design Automation Conference, Las Vegas, USA, p770-775
[36] Xianlong Hong, Gamg Huang, Yici Cai, Sheqin Dong, Jiangchun Gu, C.K. Cheng, Jun Gu, "Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan", 2000.11.5, IEEE/ACM International Conference on CAD, p8-12
