Education background
Bachelor of Computer Science, Xi'an Jiaotong University, Xi'an, China, 1999;
Ph.D. in Computer Science & Technology, Tsinghua University, Beijing, China, 2004.
Areas of Research Interests/ Research Projects
Computer-Aided Design of VLSI Circuits and Systems
Design and Analysis of Algorithms
National Natural Science Foundation of China: Research on Floorplanning Algorithms based on Timing Analysis and Optimization (2007-2009).
Research Status
My research focuses on designing fundamental algorithms in the area of VLSI design automation. I develop systems and tools to optimize the physical layout and logical design of integrated circuits (ICs). I am also working on the algorithms for combinatorial optimization and stochastic optimization. As a research associate, I visited Prof. Jason Cong's group in UCLA in 2005. During one year's stay in UCLA, I developed "3D MEVA", an evaluation model for micro-architecture of 3D ICs. Recently, I've been leading several projects on 3D ICs. Related papers are published on top conferences such as ICCAD, DAC, ASPDAC, etc.
In recent years, I have proposed several approaches to optimizing the physical design process of 2D and 3D ICs, which integrate various constraints such as timing, layout and power. To achieve efficient optimization of multiple objectives with complex constraints, an analytical optimization approach simulating the appealing and repelling force model is proposed for 3D ICs' packing process. In addition, I also proposed a novel incremental optimization process and its associated algorithms, which are helpful to the fast convergence of the complex designs.
Most of my work aims at optimizing the design process of IC layout to improve its performance, reliability and cost efficiency. This topic lies between CS and EE, and I have been collaborating with several professors in both areas, investigating ways to improve the electronic design ability, as well as the algorithms in computer science.
Honors And Awards
ASICON 2007: Best Paper Award (2007).
Academic Achievement
[1] Yuchun Ma, Xin Li, Yu Wang and Xianlong Hong. Thermal-Aware Incremental Floorplanning for 3D ICs based on MILP Formulation. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no.12, pp. 2979-2989, 2009.
[2] Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, and Jason Cong. Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, Vol.4 (4), No. 17,2008.
[3] Yuchun Ma, Xianlong Hong, Sheqin Dong, C.K. Cheng, and Jun Gu. General floorplans with L/T-shaped blocks using corner block list. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, Vol. 21, No.6, pp. 922-926, 2006.
[4] Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Dick Robert P. , Li Shang, Hai Zhou, Xianlong Hong and Qiang Zhou. 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2007), California, U.S., pp.590-597, 2007.
[5] Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, C.K. Cheng and Jun Gu. Buffer planning as an integral part of floorplanning with consideration of routing congestion. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol.24, No.4, pp.609-621, 2005.
[6] Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu. Corner Block List Representation and its Application with Boundary Constraints. Science in China Series F-Information Sciences Vol.47, No.1, pp.1-19, 2004.
[7] Yuchun Ma, Xianlong Hong, Sheqin Dong,Yici Cai, Chung-Kuan Cheng and Jun Gu. Stairway Compaction using Corner Block List and its Applications with Rectilinear Blocks. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.9. No.2, pp.199-211, 2004.
[8] Yuchun Ma, Xianlong Hong, Sheqin Dong,Song Chen,Yici Cai, Chung-Kuan Cheng and Jun Gu. Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis, Prof. 40th Design Automation Conference(DAC2003), pp.806-811, USA, 2003.
[9] Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu. An Integrated Floorplanning with an Efficient Buffer Planning Algorithm. Prof. International Symposium on Physical Design 2003(ISPD2003), pp.136-142, USA, 2003.
[10] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, and Jun Gu. Floorplanning with Abutment Constraints Based on Corner Block List. Integration, the VLSI Journal, Vol.31, pp.65-77, Netherlands, 2001.
[11] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu. Floorplanning with Boundary Constraints Using the Corner Block List(CBL) Representation. IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A, No.11, pp.2697-2704, 2001.
[12] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng and Jun Gu. Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on Corner Block List. Proc. 38th Design Automation Conference (DAC2001), pp.770-775, Las Vegas, USA, 2001.
