Education background
Bachelor of Semiconductor Device and Physics, Tsinghua University, Beijing, China, 1983;
Master of Computer Science and Technology, Tsinghua University, Beijing, China, 1986;
Ph.D. in Computer Science and Technology, University of Science and Technology of China, Hefei, China, 2007.
Social service
Institute of Software and Theory, Department of Computer Science & Technology: Director (2008-);
Academic Sub-Committee, Department of Computer Science & Technology: Member (2008-);
Integration, VLSI of Journal: Associate Editor (2009-2011);
Journal of Semiconductor (in Chinese): Member of Editorial Board (2009-2011).
Areas of Research Interests/ Research Projects
Computer-Aided Design of VLSI
Semiconductor, Micro-Electronics
National Major Science & Technology Special Project for the 11th Five-Year Plan: Development of Advanced EDA Tools and Platforms (2008-2010);
National Natural Science Foundation of China: Variation-Aware Design Technologies for Nanometer VLSI Systems (2009-2010);
National Natural Science Foundation of China: Simulation and Optimization of Power and Ground Networks on VLSI (2008-2010);
National Natural Science Foundation of China: Research on the Routing Algorithms of Nanometer-Process VLSI (2010-2012).
Research Status
My research focuses on combinatorial optimization algorithms and large-scale numerical computing analysis in VLSI design automation. Since 1986, I have been working on the interconnect analysis and optimization, P/G network design, low-power physical design, and DFM driven layout optimization. At present, our group is developing systems and tools to implement and optimize the physical design of larger-scale integrated circuits.
In the area of P/G network IR-drop noise analysis and Decap optimization, I have proposed several approaches to simulating and optimizing P/G networks. These GPU-based approaches use parallel computing methods to achieve fast and accurate simulation results for large-scale P/G networks. Related papers are published in international conferences such as ICCAD, DAC and ISPD, one of which has been nominated as DAC2009 Best Paper.
In the area of low-power physical designs, I have proposed some novel power/clock gating optimization processes/algorithms, which take trade-offs between timing delay and power in consideration to promote fast convergence of high performance and low power complex designs. Related papers are published in international conference ISPD and IEEE Trans. on VLSI.
In the area of manufacturing (DFM) driven algorithm design, my research group has, in collaboration with Synopsys Inc., proposed an efficient process-hotspot detection algorithm using range pattern matching. Related papers are published in international conference ICCAD (Best Paper Nominee) and IEEE Trans. on VLSI.
Honors And Awards
Science and Technology Progress Award by Ministry of Education, Second Class-Basic Research on Physical-Level Optimization and Verification Problems for VLSI Circuits (2006);
DAC 2009: Best Paper Nomination (2009);
ICCAD2006: Best Paper Nomination (2006);
GLVLSI 2008: Best Paper Award (2008);
Tsinghua University Outstanding Teaching Award (2000).
Academic Achievement
[1] J. Shi, Y. C. Cai, W. T. Hou, L. W. Ma, S. X.-D. Tan, P-H. Ho, X. Y. Wang, GPU friendly Fast Poisson Solver for Structured Power Grid Network Analysis, in Proc. Design Automation Conference (DAC 2009), San Francisco, USA, July 2009, PP.178-183. (Best Paper Nomination)
[2] J. Shi, Y. C. Cai, S. X.-D. Tan, X. L. Hong, High Accurate Pattern Based Precondition Method for Extremely Large Power/Ground Grid Analysis, in Prof. International Symposium on Physical Design (ISPD 2006), San Jose, USA, April 2006, PP.108-113.
[3] J. Shi, Y. C. Cai, S. X.-D. Tan, J. Fan, X. L. Hong, Pattern Based Iterative Method for Extreme Large Power/Ground Analysis, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems(TCAD), Vol.26, No.4, PP. 680-692, 2007.
[4] X. Y. Wang, Y. C. Cai, S. X.-D. Tan, Decoupling Capacitance Budgeting Aware Placement For Transient Power Supply Noise Elimination, in Proc. Integrated Circuit Computer Aided Design (ICCAD 2009), San Jose, USA, Nov. 2009, PP. 745-751.
[5] X. Y. Wang, Y. C. Cai, S. X.-D. Tan, X. L. Hong, J. Relles, An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models. in Proc. ACM/IEEE Design, Automation & Test in Europe Conference (DATE 2009), Nice, France, April 2009, PP.1190-1195.
[6] Y. C. Cai, L. Kang, J. Shi, X. L. Hong, S. X.-D. Tan, Random Walk Based Optimization Approach for Power/Ground Network, IEEE Trans. on Circuits and Systems II(TCAS-II), Vol. 55, No. 1, PP. 36-40, 2008.
[7] Cai Yici, Fu Jingjing, Hong Xianlong, S. X._D. Tan and Z. Lou Power/Ground Network Optimization Considering Decap Leakage Currents, IEEE Trans. On Circuit and System (TCAS-II), Vol.53, No. 10, pp1012-1016, 2006.
[8] Guo Liangpeng, Cai Yici, Zhou Qiang, Hong Xianlong, Performance Driven Power Gating Based on Distributed Sleep Transistor Network, Proceedings of the 2008 ACM Great Lakes Symposium on VLSI (SGLVLSI 2008), Orlando, Florida, USA, May 2008, pp255-260. (Best Paper Award)
[9] Y. C. Cai, B. Liu, Q. Zhou, X. L. Hong, Voltage Island Generation in Cell Based Dual-Vdd Design, IEICE Trans. Fundamentals of Electronic, Communications and Computer Science, Vol. E90-A, No.1, PP.267-273, 2007.
[10] W. X. Shen, Y. C. Cai, X. L. Hong, Activity and Register placement Aware Gated Clock Tree Design, in Prof. International Symposium on Physical Design (ISPD 2008), Portland, Oregon, USA, 2008, PP.182-189.
[11] Shen Weixiang, Cai Yici, Hong Xianlong, An Effective Gated Clock Network Design Based on Activity and Register Aware Placement, IEEE Trans. on Very Large Scale Integration Systems (TVLSI), (to appear).
[12] H. Yao, S. Sinha, C. Chiang, X. Hong and Y. Cai, "Efficient Process-hotspot Detection Using Range Pattern Matching," Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2006), San Jose, USA, Nov. 2006, pp. 625-632. (Best Paper Nomination)
[13] H. Yao, S. Sinha, J. Xu, C. Chiang, Y. Cai and X. Hong, "Efficient range pattern matching algorithm for process-hotspot detection," IET Circuits, Devices & Systems, Vol.2, No. 1, pp. 2-15, 2008.
[14] Y. Shen, Q. Zhou, Y. C. Cai, X. L. Hong, ECP and CMP Aware Detailed Routing Algorithms for DFM, IEEE Trans. On Very Large Scale Integration Systems (TVLSI), Vol.18, No. 1, PP.153-157, 2010.
[15] X. Hong, Y. Cai, H. Yao and D. Li, "DFM-aware Routing for Yield Enhancement," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 2006, pp. 1093-1096. (Invited paper)
[16] Jia Yanming, Cai Yici, Hong Xianlong, Dummy Fill Aware Buffer Insertion After Layer Assignment Based On An Effective Estimation Model, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E91-A, No.12, 2008, pp.3783-3792.
[17] Cai Yici, Zhou Qiang, Introduction to VLSI Design, Tsinghua University Press, Beijing, 2005 (in Chinese).
