Education background
Bachelor of Computer Science and Technology, University of Science and Technology of China, Hefei, China, 1983;
Master of Computer Science and Technology, Tsinghua University, Beijing, China, 1986;
Ph.D. in Control Theory and Control Engineering, Chinese University of Mining and Technology (Beijing), Beijing, China, 2002.
Social service
China Computer Federation: Vice Chair of Computer-Aided Design and Computer Graphics Technical Committee (2011-);
The 16th National Conference of Computer Aided Design and Graph: Program Chair (2010);
IEEE International Conference on Field-Programmable Technology (FPT) 2010: Program Chair (2010).
Areas of Research Interests/ Research Projects
Electronic Design Automation, VLSI Physical Design Algorithms
Computer Software and System
National Major Science and Technology Project: Development of Advanced EDA Tools (2008-2010);
National Natural Science Foundation of China: Research on Key Techniques of Cache Coherence Network on Chip (CC-NoC) (2009-2012);
National Natural Science Foundation of China: Reliable and Low-Power On-Chip Clock Design and Optimization Algorithms (2009-2011).
Research Status
My research focuses on algorithms in Electronic Design Automation and VLSI Physical Design Automation. I am interested in emerging fields as technology advances, such as 3D IC design automation, ultra large and mixed mode placement, interconnect planning and optimization, and programmable technology.
3D IC design is a new field which can extend Moore's Law. My research group's interests in 3D IC physical design automation aim at area, wire-length, and thermal optimization. We address the problems of runtime inefficiency and thermal issue in 3D layout. We work on novel physical design algorithms based on the hierarchical design concept and divide-and-conquer technique to reduce design complexity introduced by the 3rd dimension. As technology advances, IC goes larger and larger. We are attempting to find a fast algorithm to solve the problems in ultra-large and mixed-mode placement, such as multiple objectives, many constraints, and clock node distributions. We have proposed some methods for interconnect planning and optimization for low-power, thermal and yield-in nanometer IC design. We have also investigated in the FPGA design automation methodologies and have implemented various algorithms for technology mapping, placement and routing.
Honors And Awards
CAD Key Technologies and Applications, for Science and Technology Progress Award by City of Beijing, Second Class-Computer Aided Physical Design of Ultra-Deep, Sub-Micron SOC: Key Techniques and Applications (2007).
Academic Achievement
[1] Qiang Zhou, Xin Zhao, Yici Cai, Xainlong Hong, A MTCMOS Technology for Low-Power Physical Design,Integration, the VLSI Journal, vol.42, no. 3, pp. 340-345, 2009.
[2] Junbo Yu, Qiang Zhou, Gang Qu, Bian Jinian, Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation,IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E92-A, no.12, pp. 3151-3159, 2009.
[3] Haixia Yan, Qiang Zhou, Xianlong Hong, Thermal aware placement in 3D ICs using quadratic uniformity modeling approach,Integration, the VLSI Journal, vol. 42 no.2 pp.175-180, 2009.
[4] Junjun Gu, Gang Qu, and Qiang Zhou, Information Hiding for Trusted System Design,Proceeding of the ACM/IEEE Design Automation Conference(DAC 2009), San Francisco, CA, pp.698-701.
[5] Wang Xiaoyi, Cai Yici, Zhou Qiang, Sheldon X.-D. Tan, Decoupling Capacitance Budgeting Aware Placement For Transient Power Supply Noise Elimination,Proceedings of ACM/IEEE International Conference on Computer Aided Design(ICCAD 2009), San Jose, CA, pp. 745-751, 2009
[6] Junbo Yu, Qiang Zhou, Jinian Bian. Peak Temperature Control in Thermal-aware Behavioral Synthesis through Allocating the Number of Resources.Proceedings of IEEE Asia South Pacific Design Automation Conference(ASPDAC 2009), Yokohama, Japan, pp. 85-90, 2009.
[7] Cai Yici, Zhou Qiang, Hong Xianlong, Shi Rui, Wang Yang, Applications of Optical Proximity Correction Technology,Science In China, vol. 51, no. 2, pp. 213-224, 2008.
[8] Guo Liangpeng, Cai Yici, Zhou Qiang, Hong Xianlong, Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage,IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.8, pp. 2084-2090, 2008.
[9] Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong, A novel performance driven power gating based on distributed sleep transistor network, Proceedings of the 18th ACM Great Lakes symposium on VLSI(GLVLSI 2008), Rhode Island, USA, pp:255-260, 2008.
[10] Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian, Low power clock buffer planning methodology in F-D placement for large scale circuit design,Proceedings of IEEE Asia and South Pacific Design Automation Conference(ASPDAC 2008), Seoul, Korea, pp. 370-375.
[11] Xing Wei, Juanjuan Chen,, Qiang Zhou, Yici Cai,, Jinian Bian,, Xianlong Hong, MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation,International Conference on Field Programmable Logic and Applications( FPL 2008), Heidelberg, Germany, pp.559-562, 2008.
[12] Li Zhuoyuan, Hong Xianlong, Qiang Zhou, Shan Zeng, Bian Jinian, Wenjian Yu, Yang H.H., Pitchumani V., Chung-Kuan Cheng, Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp.645-658, 2007.
[13] Zhou Qiang, Cai Yici, Li Duo, Hong Xianlong, A yield-driven gridless router,Journal of Computer Science and Technology, vol. 22, no. 5, pp.653-660, 2007.
[14] Cai Yici, Liu Bin, Zhou Qiang, Hong Xianlong, Voltage island generation in cell based dual-Vdd design,IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no 1, pp. 267-273, 2007.
[15] Lu Yongqiang, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu, An Efficient Quadratic Placement Based On Search Space Traversing Technology,Integration, VLSI journal, vol.40, no. 3, pp. 253-260, 2007.
[16] Cai Yici, Zhou Qiang, Hong Xianlong, Shi Rui, Wang Yang, Optical Proximity Correction Technology and Applications,Science in China, Issue E Informationis, vol.37, no.12, 2007 (in Chinese).
[17] Zhou Pingqiang, Yuchun Ma, Zhuoyuan Li, Robert Dick, Li Shang, Xianlong Hong, Qiang Zhou, 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits,Proceedings of ACM/IEEE International Conference on Computer Aided Design(ICCAD 2007), San Jose, CA, pp. 590-597, 2007.
[18] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Yang, Vijay Pitchumani. Efficient Thermal-oriented 3D Floorplanning Algorithm And Thermal Via Planning For Two-stacked-die Integration.ACM Transactions on Design Automation of Electronic Systems, vol.11 no.2, pp.325-345, 2006.
[19] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng. Hierarchical 3-D Floorplanning Algorithm For Wirelength Optimization.IEEE Transactions on Circuits And Systems - I : Fundamental Theory and Applications,vol. 53, no. 12, pp.2637-2646, 2006.
[20] Cai Yici, Liu Bin, Zhou Qiang, Hong Xianlong, A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment,IEEE Transactions on CAS-II,vol.53, no. 10, pp1007-1011, 2006.
[21] Yao Hailong, Cai Yici, Zhou Qiang, Hong Xianlong, Multilevel Routing with Redundant Via Insertion,IEEE Transactions On CAS-II, vol.53, no. 10, pp.1148-1152, 2006.
[22] Cai Yici, Liu Bin, Zhou Qiang, Hong Xianlong, Priority-Based Routing Resource Assignment Considering Crosstalk,Journal of Computer Science and Technology, vol.21, no.6, pp. 913-921, 2006.
[23] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng. Integrating Dynamic Thermal Via Planning With 3D Floorplanning Algorithm.ACM/SIGDA International Symposium on Physical Design( ISPD 2006), San Jose, pp.178-185, 2006.
[24] Liu Bin, Cai Yici, Zhou Qiang, Hong Xianlong, Power Driven Placement with Layout Aware Supply Voltage Assignment for Voltage Island Generation in Dual-Vdd Designs,The Proceeding of 11th IEEE/ACM Asia & South Pacific Design Automation Conference (ASP-DAC2006), Yokohama, Japan, pp. 582-587, 2006.
[25] Zhuoyuan Li, Hiaxia Yan, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Yang, Vijay Pitchumani. Design Tools For 3D Mixed Mode Placement.IEEE International Conference on ASIC(ASICON 2005), Shanghai, vol.2 pp.792-796, 2005.
